A non-uniform memory access (NUMA) architecture in which a processor accesses a plurality of memories of which the access speeds are different is employed as an architecture that a physical machine employs.
In a physical machine that employs the NUMA architecture, data of which the access frequency of a processor is high is deployed in a memory of which the response period corresponding to a memory access request is short. In this way, a physical machine that employs the NUMA architecture can improve the overall memory access efficiency of the physical machine (that is, the response period to a memory access request can be shortened) (for example, see Japanese Laid-open Patent Publication No. 2012-247827 and Japanese Laid-open Patent Publication No. H7-191882).